In the process of creating a large integrated circuit chip design, it is quite useful and customary to partition the logic into manageable pieces and to design hierarchically. This modularity maximizes reuse and simplifies the design. Some of the design pieces or blocks might be custom designed, while others could simply be synthesized ASIC (Application Specific Integrated Circuit) blocks. If the design is to be processed by a timing analysis tool, such as a static timing analyzer, there must at least be timing information for each of the lowest level building blocks of the design. Timing information about these blocks is presented to the timing analysis tool in the form of timing rules.
There currently exist static timing analysis tools, which are commonly made available by vendors of CAE stations and software, for timing analysis. Timing analysis is performed by software which analyzes the timing relationships between logic state changes within a circuit and determines if certain timing criteria such as minimum setup and hold times have been violated. A static timing analyzer does not attempt to model the circuit as it would operate but rather attempts to analyze a circuit's temporal behavior.
Timing rules for custom design blocks are usually generated via automatic program (such as Pathmill by EPIC), by hand, or some combination of the two. The problem is that the process is error prone, since rule generation programs rely on determining circuit temporal behavior based on a sometimes faulty set of heuristics, and manual generation suffers from all the problems associated with human intervention. Therefore, the timing rule must be checked to be sure that all of the required timing relationships, such as the correct propagation paths and setup and hold tests, exist in the rule, with no unnecessary additions. Results of missing timing relationships can be disastrous. Excess timing relationships cause additional problems. Checking many large, complicated rules by hand is not a reasonable option. Thus, what is needed is a computer implemented method for verifying timing rules for an integrated circuit design.